• Introduction
  • Background & Motivation
  • Goal
  • Gap
• Details

Introduction

Background & Motivation

Bringing DNNs into various hardware is an important research area.

Two communities are optimizing DNNs for commodity devices.

• NAS: trade-off between size and acc
• Compiler: optimize the existing well-defined model by restructuring underlying tensor computations.

The actual usage workflow is first to search one model from the search space and then feed it to the optimizing compiler to meet the hardware requirement.

Goal

This paper combines neural architecture search and compiler optimization in a unified framework to achieve NAS in hardware aware manner.

• Combines the NAS and compiler optimizations to form a new space.

Gap

Few works of NAS consider the hardware behavior but have problems:

• Having complex methods for predicting the search space.
• Having a fixed pipeline and missing powerful candidate architectures.
• Limited to selecting from a pre-designed list of CNN operations.

Details

The paper union the NAS and compiler optimizations by proposing two-phase searching

1. For each model, train and propose a few transformation combinations.
2. For each transformed model, the paper uses training-free-model evaluation metrics to decide if this is illegal quickly.
3. Finally, the paper chooses the most optimized transformed model to replace the original model and compares all optimized models to find the best final model.

---

• ← Previous Post
• Next Post →